# Computer Architecture
Computer architecture defines the organization and behaviour of a computer's hardware components, emphasizing the interactions among CPU, memory, and I/O that determine performance and power efficiency.
Computer architecture encompasses the design and organization of the central processing unit (CPU), memory hierarchy, input/output systems, and the interconnections among these components. It includes instruction set architectures (ISAs), datapath design, control logic, pipelining strategies, cache hierarchies, virtual memory, memory coherence, and parallel processing models. Foundational models such as Von Neumann (shared memory for instructions and data) and Harvard (separate instruction and data memories) illustrate how architectural choices impact performance, power, and cost. Modern architectures balance latency and throughput through techniques like deep pipelines, branch prediction, cache coherence protocols, memory-level parallelism, and multi-core or many-core designs. A complete view also considers I/O subsystems, storage hierarchies, and virtualization that enable scalable, secure, and interoperable systems.
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Rel_security_architecture["security-architecture"]:::related -.-> Center
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Rel_security_automation["security-automation"]:::related -.-> Center
click Rel_security_automation "/terms/security-automation"
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🧠 Knowledge Check
🧒 Explain Like I'm 5
🧠 Computer architecture is like the blueprint for a city, deciding how buildings (processors) and roads (connections) work together to get things done efficiently.
🤓 Expert Deep Dive
## Expert Deep Dive: Computer Architecture
Modern computer architecture transcends basic component descriptions, delving into intricate layers of abstraction and optimization. At the Instruction Set Architecture (ISA) level, the fundamental divergence between RISC (e.g., ARM) and CISC (e.g., x86) paradigms dictates instruction complexity, register usage, and addressing modes, impacting both software portability and hardware implementation. The microarchitecture then realizes this ISA, employing advanced techniques such as superscalar execution, out-of-order execution (OoOE) with reorder buffers and reservation stations, and sophisticated branch prediction mechanisms (e.g., Gshare, BTB) to maximize Instruction Level Parallelism (ILP).
The memory hierarchy is a critical design space, balancing latency and throughput through multi-level caches (L1, L2, L3) managed by protocols like MESI and employing diverse replacement policies (LRU, FIFO). Beyond cache coherence, memory consistency models (sequential, relaxed) profoundly influence multi-processor programming paradigms. Parallelism is exploited at Thread-Level (TLP) and Data-Level (DLP), manifesting in multi-core designs with shared caches and NUMA architectures, and in many-core systems like GPUs utilizing SIMT execution models and massive parallelism. Interconnects, evolving from buses to sophisticated Networks-on-Chip (NoCs) with topologies like meshes and fat-trees, are vital for inter-core communication. Performance is increasingly quantified by power efficiency (Perf/Watt) and area efficiency (Perf/Area), driving innovations in DVFS, clock gating, and specialized accelerators (ASICs, FPGAs, TPUs) for heterogeneous computing. Architectural security features, such as TEEs and side-channel mitigations, are also paramount.
❓ Frequently Asked Questions
What is the difference between computer architecture and computer organization?
Computer architecture defines the high-level design and the functional capabilities of a system, while computer organization describes how the components are arranged and operate to realize those capabilities.
What are Von Neumann and Harvard architectures?
Von Neumann architecture uses a single shared memory for instructions and data; Harvard architecture uses separate memories for instructions and data, affecting bandwidth and design tradeoffs.
Why is memory hierarchy important in architecture?
A memory hierarchy (registers, L1/L2/L3 caches, main memory) hides latency and increases effective bandwidth by exploiting locality, thereby improving overall performance.